I am a Ph.D. candidate in the Concurrent VLSI Architecture group at Stanford University. My primary area of research is in design, implementation, and fabrication of high speed mixed-signal circuit architectures in deep submicron CMOS.
I am currently a visiting National Science Foundation EAPSI Fellow at Tsinghua University, Beijing, China working with Assistant Professor Baoyong Chi on low-power RF front-end circuit design for wireless endoscopes.
I will be an incoming assistant professor at Oregon State starting September, 2006.
My thesis work has been in the design of a low-power/area/complexity 20Gb/s serial link in standard CMOS. My general interests are: programmability and compensation techniques for process variation in future CMOS processes, low resolution, high sampling rate(> 20GS/s) A/D converters, and mixed-signal circuit interfaces for interdisciplinary research areas.
pchiang (at) cva.stanford.edu