High Speed Signaling


Principal Investigator: William J. Dally

With technology scaling, off-chip communication has become the bottleneck for system performance. To overcome this bottleneck, we have developed several high speed signaling techniques for off-chip communication. We developed the first simultaneous bi-directional I/O pads (1990), the first equalized high-speed CMOS link using transmit pre-emphasis (1996), the first low-power, area-efficient high-speed CMOS serial link transceiver(2000), and the fastest(20Gb/s) fully integrated CMOS transmitter to date(2003). Future work involves crosstalk cancellation between parallel I/O links, and a complete low-power/area 20Gb/s 0.13um CMOS transceiver. Research topics include:

Serial Link and Parallel Link I/O Circuit Design
Phase-Locked Loops (PLLs) and Delay-Locked Loops (DLLs) Circuit Design
Timing Acquisition, Channel Coding, Equalization
Low Power Circuit Design

This project is supported by Defense Advanced Research Projects Agency and Intel Corporation.

For problems or questions regarding this web contact Patrick Chiang.
Last updated: April 1, 2005.