Stanford Interconnection Network Research

ICN

We are developing the architectures and algorithms essential to the next generation of interconnect applications: parallel computing, network switches and routers, high-performance I/O systems, and on-chip networks.

Projects

Enabling Technology for On-Chip Networks
High-Radix System Area Networks

People

(All email addresses end in cva.stanford.edu)

Prof. William J. Dally (dally@)
James Balfour (jbalfour@)
Daniel U. Becker (dub@)
James Chen (james119@)
Nan 'Ted' Jiang (qtedq@)
George Michelogiannakis (mihelog@)

Recent Publications

George Michelogiannakis and William J Dally. Router designs for elastic buffer on-chip networks. In SC '09: Proceedings of the 2009 ACM/IEEE Conference on High Performance Computing, Networking, Storage and Analysis, 2009. [ bib | DOI | .pdf | Abstract | Slides ]

Daniel U Becker and William J Dally. Allocator implementations for network-on-chip routers. In SC '09: Proceedings of the 2009 ACM/IEEE Conference on High Performance Computing, Networking, Storage and Analysis, 2009. [ bib | DOI | .pdf | Abstract | Slides ]

George Michelogiannakis, James Balfour, and William J Dally. Elastic-buffer flow control for on-chip networks. In HPCA '09: Proceedings of the Fifteenth International Symposium on High-Performance Computer Architecture, pages 151-162, 2009. [ bib | DOI | .pdf | Abstract | Slides ]

Nan Jiang, John Kim, and William J Dally. Indirect adaptive routing on large scale interconnection networks. In ISCA '09: Proceedings of the 36th annual International Symposium on Computer Architecture, pages 220-231, 2009. [ bib | DOI | http | Abstract | Slides ]

George Michelogiannakis and William J Dally. Router designs for elastic buffer on-chip networks. Technical Report 125, Concurrent VLSI Architectures Group, Stanford University, 2009. [ bib | .pdf | Abstract ]

John Kim, William J Dally, Steve Scott, and Dennis Abts. Technology-driven, highly-scalable dragonfly topology. In ISCA '08: Proceedings of the 35th annual International Symposium on Computer Architecture, pages 77-88, 2008. [ bib | DOI | http | Abstract ]

John Kim. High-Radix Interconnection Networks. PhD thesis, Stanford University, 2008. [ bib | .pdf ]

George Michelogiannakis, James Balfour, and William J Dally. Elastic buffer networks-on-chip. Technical Report 124, Concurrent VLSI Architectures Group, Stanford University, 2008. [ bib | .pdf | Abstract ]

John D Owens, William J Dally, Ron Ho, D N Jayasimha, Stephen W Keckler, and Li-Shiuan Peh. Research challenges for on-chip interconnection networks. IEEE Micro, 27(5):96-108, 2007. [ bib | DOI | http | Abstract ]

John Kim, James Balfour, and William J Dally. Flattened butterfly topology for on-chip networks. In MICRO 40: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, 2007. [ bib | .pdf | Abstract ]

A comprehensive list of publications can be found here (also available in BibTeX format).