Stanford Interconnection Networks Research

Stanford Interconnection Network Research

We are developing the architectures and algorithms essential to the next generation of interconnect applications: parallel computing, network switches and routers, high-performance I/O systems, and on-chip networks. Recent results and ongoing projects include:

On-Chip Interconnection Networks
High-Radix System Area Networks

Previous Projects

High-Radix Routers
Randomized routing on k-ary n-cubes
Worst-case traffic for oblivious routing functions
Hierarchical networks
Constrained switch scheduling
Network Topology Optimization

Members

Former Members

This work is supported by:

Recent Publications

Gupta, Amit K and Dally, William J., "Topology Optimization of Interconnection Networks", Computer Architecture Letters, Volume 4, July 2005.
Kim, John, Dally, William J., Towles, Brian, and Gupta, Amit K., "Microarchitecture of a High-Radix Router", Proceedings. 32th Annual International Symposium on Computer Architecture(ISCA), June 2005, pp. 420-431.
Singh, Arjun. Load-Balanced Routing in Interconnection Networks. Stanford University Ph.D. Thesis, 2005.
Towles, Brian. Distributed Router Fabrics. Stanford University Ph.D. Thesis, 2005.
Arjun Singh and William J. Dally,"Buffer and Delay Bounds in High Radix Interconnection Networks", Computer Architecture Letters, Volume 3, December, 2004.
Arjun Singh, William J. Dally, Amit K. Gupta and Brian Towles,"Adaptive Channel Queue Routing on k-ary n-cubes", ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), Barcelona, Spain, June, 2004.
Arjun Singh, William J. Dally, Brian Towles and Amit K. Gupta,"Globally Adaptive Load-Balanced Routing on Tori", Computer Architecture Letters, Volume 3, March, 2004.
Towles, B., and Dally, W.J. "Guaranteed scheduling for switches with configuration overhead," IEEE/ACM Transactions on Networking, 11(5), pp. 835-847, October, 2003.
Singh, A., Dally, W.J., Gupta, A.K., and Towles, B., GOAL: a load-balanced adaptive routing algorithm for Torus networks, Proceedings. 30th Annual International Symposium on Computer Architecture, June 2003, pp. 194- 205.
Towles, Brian, Dally, William J., Boyd, Stephen P., "Throughput-Centric Routing Algorithm Design," ACM Symposium on Parallel Algorithms and Architectures (SPAA), San Diego, CA, June, 2003.
Gupta, Amit K., Dally, William J., Singh, Arjun, and Towles, Brian, "Scalable Opto-Electronic Network (SOEnet)," 10th Symposium on High Performance Interconnects (HotI X), Stanford, CA, August, 2002.
Singh, Arjun, Dally, William J., Towles, Brian, and Gupta, Amit K., "Locality-Preserving Randomized Oblivious Routing on Torus Networks," (preliminary version) ACM Symposium on Parallel Algorithms and Architectures (SPAA), Winnipeg, Manitoba, Canada, August, 2002.
Towles, Brian and Dally, William J. , "Worst-case Traffic for Oblivious Routing Functions," (preliminary version) ACM Symposium on Parallel Algorithms and Architectures (SPAA), Winnipeg, Manitoba, Canada, August, 2002.
Towles, Brian and Dally, William J., "Guaranteed Scheduling for Switches with Configuration Overhead," INFOCOM 2002, New York, NY, June 2002.
Towles, Brian and Dally, William J. , "Worst-case Traffic for Oblivious Routing Functions," Computer Architecture Letters, Vol. 1, Feb. 2002.
Dally, William J., and Towles, Brian, "Route Packets, Not Wires: On-Chip Interconnection Networks," in Proceedings of the 38th Design Automation Conference (DAC), Las Vegas, NV, June 2001.
Mizuno, Masayuki, Dally, William J., and Onishi, Hideaki, "Elastic Interconnects: Repeater-inserted Long Wiring Capable of Compressing and Decompressing Data," in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 346-347, 464, 2001.
Peh, Li-Shiuan. Flow Control and Micro-Architectural Mechanisms for Extending the Performance of Interconnection Networks. Stanford University Ph.D. Thesis, August 2001.
Peh, Li-Shiuan and Dally, William J., "A Delay Model for Router Micro-architectures," IEEE Micro, vol. 21, issue 1, pp. 26-34, Jan/Feb 2001.
Peh, Li-Shiuan and Dally, William J., "A Delay Model and Speculative Architecture for Pipelined Routers," in Proceedings of the 7th International Symposium on High-Performance Computer Architecture, pp. 255-266, Monterrey, Mexico, Jan. 2001.
Peh, Li-Shiuan and Dally, William J., "A Delay Model for Router Micro-Architectures," in Proceedings of Hot Interconnects 8, Stanford, CA, August 2000.
Peh, Li-Shiuan and Dally, William J., "Flit-Reservation Flow Control," in Proceedings of the 6th International Symposium on High-Performance Computer Architecture, pp. 73-84, Toulouse, France, Jan. 1999.

Reliable Router

Dennison, Larry R. . The Reliable Router: An Architecture for Fault Tolerant Interconnect. PhD Thesis, Masschusetts Institute of Technology, June 1996.
Dennison, Larry R., Dally, William J., and Xanthopoulos, Duke, "Low-Latency Plesiochronous Data Retiming," in Proceedings of the 1995 Advanced Research in VLSI Conference, Chapel Hill NC, March 1995.
Xanthopoulos, Thucydides. Fault Tolerant Adaptive Routing in Multicomputer Networks. SM Thesis, Massachusetts Institute of Technology, Department of Electrical Engineering, February, 1995.
Dally, William J., Dennison, Larry R., Harris, David, Kan, Kinhong, and Xanthopoulos, Thucydides, "Architecture and Implementation of the Reliable Router," in Proceedings of Hot Interconnects II, Stanford CA, August 1994.
Dally, William J., Dennison, Larry R., Harris, David, Kan, Kinhong, and Xanthopoulos, Thucydides, "The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers," in Proceedings of the First International Parallel Computer Routing and Communication Workshop, Seattle WA, May 1994.
Dennison, Larry R., Lee, Whay S., and Dally, William J., "High-Performance Bidirectional Signalling in VLSI Systems," in Proceedings of the 1993 Symposium on Research on Integrated Systems, Seattle WA, January 1993.
Dennison, Larry R. Reliable Interconnection Networks for Parallel Computers. SM Thesis, Masschusetts Institute of Technology, January 1991.

Virtual-Channel Flow Control and Wire-Efficient Networks

Dally, William J. and Aoki, Hiromichi, "Deadlock-free Adaptive Routing in Multicomputer Networks Using Virtual Channels," IEEE Trans. on Parallel and Distributed Systems, 4(4):466-475, April 1993.

Dally, William J., "Virtual-channel Flow Control," IEEE Trans. on Parallel and Distributed Systems, 3(2):194-205, March 1992.

Dally, William J., "Express Cube: Improving the Performance of k-ary n-cube Interconnection Networks," IEEE Trans. on Computers, C-40(9):1016-1023, Sept. 1991.

Dally, William J., "Performance Analysis of k-ary n-cube Interconnection Networks," IEEE Trans. on Computers, C-39(6):775-785, June 1990.
Dally, William J., "Virtual-channel Flow Control," in Proceedings of the 17th Int. Symp. on Computer Architecture, ACM SIGARCH vol. 18, no. 2, May 1990, pp. 60-68.
Dally, William J., "Wire-efficient VLSI Multiprocessor Communication Networks," in Proceedings of the 1987 Stanford Conference on Advanced Research in VLSI, pp. 391-415, Stanford, CA, 1987.
Dally, William J. and Seitz, Charles L., "Deadlock Free Message Routing in Multiprocessor Interconnection Networks," IEEE Trans. on Computers, C-36(5):547-553, May, 1987.
Dally, William J. and Seitz, Charles L., "The Torus Routing Chip," Journal of Parallel and Distributed Computing, 1(3):187-196, 1986.

Stanford Interconnection Network Research

Members

Recent Publications

Reliable Router

Virtual-Channel Flow Control and Wire-Efficient Networks

Back to Top

For problems or questions regarding this web contact agupta@cva.stanford.edu.
Last updated: March 2, 2006.

Stanford Interconnection Network Research

Members

Recent Publications

Reliable Router

Virtual-Channel Flow Control and Wire-Efficient Networks

Back to Top

For problems or questions regarding this web contact agupta@cva.stanford.edu. Last updated: March 2, 2006.

For problems or questions regarding this web contact agupta@cva.stanford.edu.
Last updated: March 2, 2006.