George Michelogiannakis, James Balfour, and William J Dally. Elastic-buffer flow control for on-chip networks. In HPCA '09: Proceedings of the Fifteenth International Symposium on High-Performance Computer Architecture, pages 151-162, 2009. [ bib | DOI | .pdf | Abstract ]

Nan Jiang, John Kim, and William J Dally. Indirect adaptive routing on large scale interconnection networks. In ISCA '09: Proceedings of the 36th annual International Symposium on Computer Architecture, pages 220-231, 2009. [ bib | DOI | http | Abstract ]

George Michelogiannakis and William J Dally. Router designs for elastic buffer on-chip networks. In SC '09: Proceedings of the 2009 ACM/IEEE Conference on High Performance Computing, Networking, Storage and Analysis, 2009. [ bib | DOI | .pdf | Abstract ]

Daniel U Becker and William J Dally. Allocator implementations for network-on-chip routers. In SC '09: Proceedings of the 2009 ACM/IEEE Conference on High Performance Computing, Networking, Storage and Analysis, 2009. [ bib | DOI | .pdf | Abstract ]

George Michelogiannakis and William J Dally. Router designs for elastic buffer on-chip networks. Technical Report 125, Concurrent VLSI Architectures Group, Stanford University, 2009. [ bib | .pdf | Abstract ]

John Kim, William J Dally, Steve Scott, and Dennis Abts. Technology-driven, highly-scalable dragonfly topology. In ISCA '08: Proceedings of the 35th annual International Symposium on Computer Architecture, pages 77-88, 2008. [ bib | DOI | http | Abstract ]

John Kim. High-Radix Interconnection Networks. PhD thesis, Stanford University, 2008. [ bib | .pdf ]

George Michelogiannakis, James Balfour, and William J Dally. Elastic buffer networks-on-chip. Technical Report 124, Concurrent VLSI Architectures Group, Stanford University, 2008. [ bib | .pdf | Abstract ]

John D Owens, William J Dally, Ron Ho, D N Jayasimha, Stephen W Keckler, and Li-Shiuan Peh. Research challenges for on-chip interconnection networks. IEEE Micro, 27(5):96-108, 2007. [ bib | DOI | http | Abstract ]

John Kim, James Balfour, and William J Dally. Flattened butterfly topology for on-chip networks. In MICRO 40: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, 2007. [ bib | .pdf | Abstract ]

John Kim, William J Dally, and Dennis Abts. Flattened butterfly: A cost-efficient topology for high-radix networks. In ISCA '07: Proceedings of the 34th annual International Symposium on Computer Architecture, pages 126-137, 2007. [ bib | DOI | http | Abstract ]

Amit K Gupta and William J Dally. Topology optimization of interconnection networks. Computer Architecture Letters, 5(1):10-13, 2006. [ bib | DOI | http | Abstract ]

James Balfour and William J Dally. Design tradeoffs for tiled cmp on-chip networks. In ICS '06: Proceedings of the 20th annual International Conference on Supercomputing, pages 187-198, 2006. [ bib | DOI | http | Abstract ]

John Kim, William J Dally, and Dennis Abts. Adaptive routing in high-radix clos network. In SC '06: Proceedings of the 2006 ACM/IEEE Conference on Supercomputing, 2006. [ bib | DOI | http | Abstract ]

Steve Scott, Dennis Abts, John Kim, and William J Dally. The blackwidow high-radix clos network. In ISCA '06: Proceedings of the 33rd annual International Symposium on Computer Architecture, pages 16-28, 2006. [ bib | DOI | http | Abstract ]

John Kim, William J Dally, Brian Towles, and Amit K Gupta. Microarchitecture of a high-radix router. In ISCA '05: Proceedings of the 32nd annual International Symposium on Computer Architecture, pages 420-431, 2005. [ bib | DOI | http | Abstract ]

Brian Towles. Distributed Router Fabrics. PhD thesis, Stanford University, 2005. [ bib | .pdf ]

Arjun Singh. Load-Balanced Routing in Interconnection Networks. PhD thesis, Stanford University, 2005. [ bib | .pdf ]

Arjun Singh and William J Dally. Buffer and delay bounds in high radix interconnection networks. Computer Architecture Letters, 3(1):8-11, 2004. [ bib | DOI | http | Abstract ]

Arjun Singh, William J Dally, Brian Towles, and Amit K Gupta. Globally adaptive load-balanced routing on tori. Computer Architecture Letters, 3(1):2-5, 2004. [ bib | DOI | http | Abstract ]

Arjun Singh, William J Dally, Amit K Gupta, and Brian Towles. Adaptive channel queue routing on k-ary n-cubes. In SPAA '04: Proceedings of the 16th Annual ACM Symposium on Parallelism in Algorithms and Architectures, pages 11-19, 2004. [ bib | DOI | http | Abstract ]

Arjun Singh and William J Dally. Delay and buffer bounds in high radix interconnection networks. Technical report, Concurrent VLSI Architectures Group, Stanford University, 2004. [ bib | .pdf | Abstract ]

Arjun Singh and William J Dally. Globally adaptive load-balanced routing on k-ary n-cubes. Technical report, Concurrent VLSI Architectures Group, Stanford University, 2004. [ bib ]

Brian Towles and William J Dally. Guaranteed scheduling for switches with configuration overhead. IEEE/ACM Transactions on Networking, 11(5):835-847, 2003. [ bib | DOI | http | Abstract ]

Arjun Singh, William J Dally, Amit K Gupta, and Brian Towles. Goal: a load-balanced adaptive routing algorithm for torus networks. In ISCA '03: Proceedings of the 30th annual International Symposium on Computer Architecture, pages 194-205, 2003. [ bib | DOI | http ]

Brian Towles, Stephen P Boyd, and William J Dally. Throughput-centric routing algorithm design. In SPAA '03: Proceedings of the 15th Annual ACM Symposium on Parallelism in Algorithms and Architectures, pages 200-209, 2003. [ bib | DOI | http | Abstract ]

Brian Towles and William J Dally. Worst-case traffic for oblivious routing functions. Computer Architecture Letters, 1(1):4-7, 2002. [ bib | DOI | http | Abstract ]

Amit K Gupta, William J Dally, Arjun Singh, and Brian Towles. Scalable opto-electronic network (soenet). In HOTI '02: Proceedings of the 10th Symposium on High Performance Interconnects, pages 71-76, 2002. [ bib | DOI | http | Abstract ]

Brian Towles and William J Dally. Guaranteed scheduling for switches with configuration overhead. In INFOCOM '02: Proceedings of the 21st Annual Joint Conference of the IEEE Computer and Communications Societies, pages 342-351, 2002. [ bib | DOI | http | Abstract ]

Brian Towles and William J Dally. Worst-case traffic for oblivious routing functions. In SPAA '02: Proceedings of the 14th Annual ACM Symposium on Parallelism in Algorithms and Architectures, pages 1-8, 2002. [ bib | DOI | http | Abstract ]

Arjun Singh, William J Dally, Brian Towles, and Amit K Gupta. Locality-preserving randomized oblivious routing on torus networks. In SPAA '02: Proceedings of the 14th Annual ACM Symposium on Parallelism in Algorithms and Architectures, pages 9-13, 2002. [ bib | DOI | http | Abstract ]

Li-Shiuan Peh and William J Dally. A delay model for router microarchitectures. IEEE Micro, 21(1):26-34, 2001. [ bib | DOI | http | Abstract ]

William J Dally and Brian Towles. Route packets, not wires: On-chip inteconnection networks. In DAC '01: Proceedings of the 38th Conference on Design Automation, pages 684-689, 2001. [ bib | DOI | http | Abstract ]

Li-Shiuan Peh and William J Dally. A delay model and speculative architecture for pipelined routers. In HPCA '01: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture, pages 255-266, 2001. [ bib | DOI | .pdf | Abstract ]

Li-Shiuan Peh. Flow Control and Micro-Architectural Mechanisms for Extending the Performance of Interconnection Networks. PhD thesis, Stanford University, 2001. [ bib | .pdf ]

Brian Towles. Finding worst-case permutations for oblivious routing algorithms. Technical Report 121, Concurrent VLSI Architectures Group, Stanford University, 2001. [ bib | .pdf | Abstract ]

Li-Shiuan Peh and William J Dally. A delay model for router microarchitectures. In HOTI '00: Proceedings of the 8th Symposium on High Performance Interconnects, 2000. [ bib ]

Li-Shiuan Peh and William J Dally. Flit-reservation flow control. In HPCA '00: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, pages 73-84, 2000. [ bib | DOI | http | Abstract ]

William J Dally and Hiromichi Aoki. Deadlock-free adaptive routing in multicomputer networks using virtual channels. IEEE Transactions on Parallel and Distributed Systems, 4(4):466-475, 1993. [ bib | DOI | http | Abstract ]

William J Dally. Virtual-channel flow control. IEEE Transactions on Parallel and Distributed Systems, 3(2):194-205, 1992. [ bib | DOI | http | Abstract ]

William J Dally. Express cubes: Improving the performance of k-ary n-cube interconnection networks. IEEE Transactions on Computers, 40(9):1016-1023, 1991. [ bib | DOI | http | Abstract ]

William J Dally. Performance analysis of k-ary n-cube interconnection networks. IEEE Transactions on Computers, 39(6):775-785, 1990. [ bib | DOI | http | Abstract ]

William J Dally. Virtual-channel flow control. In ISCA '90: Proceedings of the 17th annual International Symposium on Computer Architecture, pages 60-68, 1990. [ bib | DOI | http | Abstract ]

William J Dally and Charles L Seitz. Deadlock-free message routing in multiprocessor interconnection networks. IEEE Transactions on Computers, 36(5):547-553, 1987. [ bib | DOI | http | Abstract ]

William J Dally. Wire-efficient vlsi multiprocessor communication networks. In Proceedings of the 1987 Stanford Conference on Advanced Research in VLSI, pages 391-415, 1987. [ bib ]

William J Dally and Charles L Seitz. The torus routing chip. Journal of Parallel and Distributed Computing, 1(4):187-196, 1986. [ bib | DOI | .pdf | Abstract ]

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