The Reliable Router

A Reliable and High Performance Communication Substrate for Parallel Computers

Project Summary

Other unique features of the Reliable Router include a full-featured diagnostic interface, a low-latency plesiochronous physical channel architecture, and simultaneous bidirectional signalling. Relevant references are listed in the Publications section.

The target clock frequency of the Reliable Router is 100 MHz. Unidirectional link bandwidth is expected to reach 3.2 Gbit/sec. The estimated die size is approximately 15mm x 16mm and the estimated transistor count is 600,000. The RR will be fabricated by MOSIS in a 1 micron, 3-metal-layer process. The planned tapeout date is January 31st 1995.

Publications

• "The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers". Appears in the Proceedings of the First International Parallel Computer Routing and Communication Workshop, Seattle WA, May 1994.
• "Architecture and Implementation of the Reliable Router". Appears in the Proceedings of Hot Interconnects II, Stanford CA, August 1994.
• "Low-Latency Plesiochronous Data Retiming". To appear in the Proceedings of the 1995 Advanced Research in VLSI Conference, Chapel Hill NC, March 1995.
• "High-Performance Bidirectional Signalling in VLSI Systems". Appears in the Proceedings of the 1993 Symposium on Research on Integrated Systems, Seattle WA, January 1993.

The Reliable Router Team

Faculty Supervisor

Graduate Students

Undergraduate Students

Past Members