The Reliable Router

A Reliable and High Performance Communication Substrate for Parallel Computers

Project Summary

The Reliable Router (RR) is a high-performance routing chip currently under development at the MIT Concurrent VLSI Architecture Group. The chip is targeted to two-dimensional network topologies. The RR uses Adaptive Routing in combination with a Unique Token Protocol to tolerate a single non-transient node or link failure anywhere in the network without interruption of service.

Other unique features of the Reliable Router include a full-featured diagnostic interface, a low-latency plesiochronous physical channel architecture, and simultaneous bidirectional signalling. Relevant references are listed in the Publications section.

The target clock frequency of the Reliable Router is 100 MHz. Unidirectional link bandwidth is expected to reach 3.2 Gbit/sec. The estimated die size is approximately 15mm x 16mm and the estimated transistor count is 600,000. The RR will be fabricated by MOSIS in a 1 micron, 3-metal-layer process. The planned tapeout date is January 31st 1995.


The Reliable Router Team

Faculty Supervisor

Bill Dally

Graduate Students

Larry Dennison, Duke Xanthopoulos

Undergraduate Students

Jeff Bowers, Dan Hartman

Past Members

Kin Hong Kan, David Harris, Ivan Oei, Peter Nuth