VLSI Design and Verification of the Imagine Processor.

Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, and Brian Towles
Stanford University
Computer Systems Laboratory

To appear in the Proceedings of International Conference on Computer Design, September 16-18, 2002, Freiburg, Germany.


The Imagine stream processor is a 21 million transistor chip implemented by a collaboration between Stanford Unversity and Texas Instruments in a 1.5V 0.15 micron process with five layers of aluminum metal. The VLSI design, clocking, and verification methodologies for the Imagine processor are presented. These methodologies enabled a small team of graduate students with limited resources to design a high-performance media processor in a modern ASIC flow.


Brucek Khailany