The Imagine Stream Processor

Ujval Kapasi, William J. Dally, Scott Rixner, John D. Owens, and Brucek Khailany
Stanford University
Computer Systems Laboratory

Appears in the Proceedings of International Conference on Computer Design, September 16-18, 2002, Freiburg, Germany.


The Imagine Stream Processor is a single-chip programmable media processor with 48 parallel ALUs. At 400MHz, this translates to a peak arithmetic rate of 16GFLOPS on single-precision data and 32GOPS on 16-bit fixed-point data. The scalability of Imagine's programming model and architecture enable it to achieve such high arithmetic rates. Imagine executes applications that have been mapped to the stream programming model. The stream model decomposes applications into a set of computation kernels that operate on data streams. This mapping exposes the inherent locality and parallelism in the application, and Imagine exploits the locality and parallelism to provide a scalable architecture that supports 48 ALUs on a single chip. This paper presents the Imagine architecture and programming model in the first half, and explores the scalability of the Imagine architecture in the second half.


BibTeX Entry

  author =     {Ujval Kapasi and William J. Dally and Scott Rixner and
               John D. Owens and Brucek Khailany},
  title =      {The {I}magine Stream Processor},
  booktitle =  {Proceedings 2002 IEEE International Conference on
                Computer Design},
  pages =      {282--288},
  year =       {2002},
  OPTaddress = {Freiburg, Germany},
  month =       sep,

Ujval Kapasi