People of CVA

Group Leader

Professor William J. Dally

Support Staff

 

Graduate Students

Name

Contact Info

Thesis Dissertation


James Balfour

jbalfour@cva

Energy Efficient Embedded Processor Architectures


Daniel Becker

dub@cva

Interconnection Networks


David Black-Schaffer

davidbbs@cva

Block Parallel Programming for Real-Time Applications on Multi-core Processors


James Chen

james119@stanford

Low Swing Circuits


Abhishek Das

abhishek@cva

Compilation methods to efficiently allocate resources in a streaming processor


Paul Hartke

phartke@cva

A Custom computing Engine to Accelerate Dynamic Programming with an Application to DNA Sequence Alignment


Curt Harting

charting@cva

Energy Efficient Embedded Processor Architectures


Ted Jiang

qtedq@cva

Interconnection Networks


Oren Kerem

orenk@cva

Hardware and software techniques for efficient use of on-chip memory in parallel architectures


Tim Knight

tjk@cva

Stream architecture, languages and compilers for stream architectures

George Michelogiannakis

mihelog@stanford

Interconnection Networks


Jiyoung Park

jypark@cva

Compilers and computer architecture


Jongsoo Park

jongsoo@stanford

Compilers and computer architecture


Vishal Parikh

vparikh1@cva

Energy Efficient Embedded Processor Architectures


Manman Ren

mmren@cva

Compilers for streaming processors and machines


David Sheffield

dsheffie@cva

Energy Efficient Embedded Processor Architectures

Recent Alumni

Name

Location

Contact Information

Degree Year

Thesis

Apple
davidbbs@cva.stanford.edu
2008

John Kim

 

jjk12@cva.stanford.edu

2008

High-Radix Interconnection Networks

Amit Gupta

Google

agupta@cva.stanford.edu

2007

Hybrid Topologies in Interconnection Networks

Dr. Jung-Ho Ahn

H.P. Labs

gajh@cva.stanford.edu

2007

Streams in Multi-Node Memory System

Prof. Mattan Erez

UT Austin

merez@cva.stanford.edu

2006

Merrimac Streaming Supercomputer

Prof. Patrick Chiang

Oregon State

pchiang@cva.stanford.edu

2006

Precision Clock Synthesis for Next Generation High Speed Serial Links

Nuwan Jayasena

Nvidia

jayasena@cva.stanford.edu

2005

Memory Hierarchy Design for Stream Computing

Andrew Chang

Cadence Design Systems

achang@cva.stanford.edu

2004

VLSI Datapath Custom Cell Optimization

Dr. Arjun Singh

Google

arjunsingh@gmail.com

2005

Load-Balanced Routing in Interconnection Networks

Professor Kelly Shaw

University of Richmond

kshaw@richmond.edu

2005

Resource Management in Single-Chip Multiprocessors

Dr. Sarah Harris

Harvey Mudd

sharris@odin.ac.hmc.edu

2005

Synergistic Caching in Single-Chip Multiprocessors

Dr. Brian Towles

D. E. Shaw

btowles@cva.stanford.edu

2005

Distributed Router Fabrics

Dr. Ujval Kapasi

Stream Processors

ujk@cva.stanford.edu

2004

Conditional Techniques for Stream Processing Kernels

Dr. Brucek Khailany

Stream Processors

khailany@cva.stanford.edu

2003

The VLSI Implementation and Evaluation of Area- and Energy-Efficient Streaming Media Processors

Former Members

Technical Staff

Visiting Scientists


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