CVA Members and Alumni


Group Leader

Professor William J. Dally


Current Graduate Students

Name

Contact Info

Research Topic

Subhasis Das

subhasis@cva

Energy-Efficient High Performance Processor Architectures

Milad Mohammadi

milad@cva

Energy-Efficient High Performance Processor Architectures

Albert Ng

albertng@cva

Energy-Efficient High Performance Processor Architectures

Nic McDonald

nmcdonal@cva

Network Interfaces for Distributed Systems

Song Han

songhan@cva

Efficient Deep Learning Algorithm and Hardware Architecture


Support Staff

Sue George
William Gates Building # 303
suegeorge AT cs DOT stanford DOT edu
Tel: (650) 725-2340


Recent Alumni

Name

Location

Contact Information

Degree Year

Thesis

Nan Jiang

Nvidia
qtedq@cva.stanford.edu
2013

Curt Harting

Google
charting@cva.stanford.edu
2012

Daniel Becker

Apple
dub@cva.stanford.edu
2012

George Michelogiannakis

Lawrence Berkeley National Labs
mihelog@cva.stanford.edu
2012

James Chen

McKinsey
james119@cva.stanford.edu
2012

Jongsoo Park

Intel
jongsoo@cva.stanford.edu
2011

James Balfour

Nvidia
jbalfour@cva.stanford.edu
2009

Jiyoung Park

jypark@cva.stanford.edu
2009

Manman Ren

Intel
mmren@cva.stanford.edu
2008
Compilers for streaming processors and machines
Uppsala University
davidbbs@cva.stanford.edu
2008
Abhishek Das
Cuil
abhishek@cva.stanford.edu
2008
Compilation methods to efficiently allocate resources in a streaming processor

John Kim

KAIST

jjk12@cva.stanford.edu

2008

High-Radix Interconnection Networks

Tim Knight

 

tjk@cva.stanford.edu

2007

Stream architecture, languages and compilers for stream architectures

Amit Gupta

Google

agupta@cva.stanford.edu

2007

Hybrid Topologies in Interconnection Networks

Jung-Ho Ahn

Seoul National University

gajh@cva.stanford.edu

2007

Memory and Control Organizations of Stream Processors

Prof. Mattan Erez

UT Austin

merez@cva.stanford.edu

2006

Merrimac Streaming Supercomputer

Prof. Patrick Chiang

Oregon State

pchiang@cva.stanford.edu

2006

Precision Clock Synthesis for Next Generation High Speed Serial Links

Nuwan Jayasena

Nvidia

jayasena@cva.stanford.edu

2005

Memory Hierarchy Design for Stream Computing

Andrew Chang

Cadence Design Systems

achang@cva.stanford.edu

2004

VLSI Datapath Custom Cell Optimization

Dr. Arjun Singh

Google

arjunsingh@gmail.com

2005

Load-Balanced Routing in Interconnection Networks

Professor Kelly Shaw

University of Richmond

kshaw@richmond.edu

2005

Resource Management in Single-Chip Multiprocessors

Dr. Sarah Harris

Harvey Mudd

sharris@odin.ac.hmc.edu

2005

Synergistic Caching in Single-Chip Multiprocessors

Dr. Brian Towles

D. E. Shaw Research

btowles@cva.stanford.edu

2005

Distributed Router Fabrics

Dr. Ujval Kapasi

Stream Processors

ujk@cva.stanford.edu

2004

Conditional Techniques for Stream Processing Kernels

Dr. Brucek Khailany

Stream Processors

khailany@cva.stanford.edu

2003

The VLSI Implementation and Evaluation of Area- and Energy-Efficient Streaming Media Processors


Former Members


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