· Harris, Sarah. Synergistic Caching in Single-Chip Multiprocessors. Stanford University Ph.D. Thesis, 2005.
· Shaw, Kelly. Resource
Management in Single-Chip Multiprocessors Stanford University
Ph.D. Thesis, 2005.
- Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh,
and Mark Horowitz.
A
20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly
Drive the Output Multiplexer. IEEE Journal of Solid
State Circuits, Vol. 4, No. 4, April 2005.
- Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh,
and Mark Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an
LC-PLL to Directly Drive the Output Multiplexer. IEEE
Symposium on VLSI Circuits, Honolulu, Hawaii, June 15-19, 2004.
- Patrick Chiang, William J. Dally, Ming-Ju E. Lee. A 20Gb\ /s 0.13um CMOS Serial Link,
IEEE Hotchips 2002, Stanford, CA, Aug. 18-20,
2002.
- M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan,
John H. Edmondson, John Poulton: CMOS High-Speed I/Os - Present and Future,
Proceedings of the IEEE International Conference on Computer Design, 2003,
pp. 454-461.
- Ng, H-T,
Lee, M.-J., Farjad-Rad, R., Senthinathan,
R., Dally, W.,
Nguyen, A., Rathi, R., Greer, T., Poulton, J., Edmondson, J., and Tran, J., "A 33mW 622 Mb/s-8Gb/s CMOS CDR for Highly
Integrated I/Os," 2003 IEEE Symposium on VLSI
Circuits, June 2003.
- Lee,
M.-J. Edward, Dally, William J., Greer, Trey, Ng, Hiok-Tiaq, Farjad-Rad, Ramin, Poulton, John, Senthinathan, Ramesh. Jitter transfer characteristics of delay-locked loops
theories and design techniques. IEEE Journal of
Solid-State Circuits, 38(4), pp. 614-621, April, 2003.
- M.-J.
Edward Lee, William J. Dally, John Poulton, Trey Greer, John Edmondson, Ramin Farjad-Rad, Hiok-Tiaq Ng, Rohit Rathi, Ramesh Senthinathan., A Second-Order Semi-Digital Clock Recovery Circuit
Based on Injection Locking, 2003 IEEE International
Solid State Circuits Conference Digest of Technical Papers, San Francisco,
CA, February, 2003.
- Lee,
M.-J. Edward, Dally, William J., Greer, Trey, Ng, Hiok-Tiaq, Farjad-Rad, Ramin, Poulton, John, Senthinathan, Ramesh. A low-power multiplying DLL for low-jitter
multigigahertz clock generation in highly integrated digital chips. IEEE Journal of Solid-State Circuits, 37(12), pp. 1804-1812, December,
2002.
- Ming-Ju Edward Lee, William J. Dally, John w. Poulton, Patrick Chiang, Stephen F.
Greenwood. An 84-mW 4Gb/s Clock and Data Recovery Circuit for
Serial Link Applications. VLSI Circuits Symposium,
Kyoto, Japan, June 2001.
- Ming-Ju Edward Lee, William Dally, Patrick Chiang. Low-Power Area-Efficient High-Speed I/O Circuit
Techniques. IEEE Journal of Solid-State Circuits,
November 2000, Vol. 35, No. 11, pp. 1591-1599.
- Ming-Ju Edward Lee, William Dally, Patrick Chiang. A 90mW 4Gb/s Equalized I/O Circuit with Input Offset
Cancellation. International Solid State Circuits
Conference, San Francisco, February 2000, TP 15.3.
- William Dally, Ming-Ju Edward Lee, Fu-Tai An, John Poulton, Steve Tell High-Performance Electrical Signaling Fifth International Conference on Massively Parallel
Processing, 15-17 Jun 1998 pp
11-16
Imagine publications have moved to the Imagine project page.
- Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally, "Fault Tolerance Techniques for the Merrimac
Streaming Supercomputer", SC|05, November 12-18
2005, Seattle, Washington, USA.
- Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. Dally, Eric Darve, Analysis and Performance Results of a Molecular
Modeling Application on Merrimac, Super Computing 2004, November
2004, Pittsburgh, Pennsylvania, USA.
- Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, and William J. Dally. Stream Register Files with Indexed Access.
Tenth International Symposium on High Performance Computer Architecture,
Madrid, Spain, February 2004.
- William J. Dally, Patrick Hanrahan, Mattan Erez, Timothy J. Knight,
Francois Labonte, Jung-Ho Ahn, Nuwan Jayasena, Ujval J. Kapasi, Abhishek Das, Jayanth Gummanraju, and Ian
Buck. "Merrimac: Supercomputing with Streams",
Super Computing 2003, November 2003, Phoenix, Arizona.
· Jayasena, Nuwan. Memory Hierarchy Design for Steram Computing, Stanford University Ph.D. Thesis, 2005.
- Keckler, Stephen W., Chang, Andrew., Lee, Whay Sing, Chatterjee, Sandeep, and Dally, William J., "Concurrent Event Handling through
Multithreading" , IEEE Transactions on Computers , Vol 48, No 9, September 1999. pp. 903-916. Abstract
- Lee, Whay Sing, Dally, William J., Keckler, Stephen W., Carter, Nicholas
P., and Chang, Andrew, "Efficient Protected Message Interface in the MIT
M-Machine", IEEE Computer Special Issue on
Design Challenges for High Performance Network Interfaces , November
1998. pp 69-75. Abstract
- Chang,
Andrew, Dally, William J., Keckler, Stephen W., Carter, Nicholas
P., and Lee, Whay Sing, "The Effects of Explictly Parallel Mechanisms on
the Multi-ALU Processor Cluster Pipeline", 1998
International Conference on Computer Design , Austin, TX, October
1998. pp 474-481. Abstract
- Keckler, Stephen W., Dally, William J., Maskit, Daniel, Carter, Nicholas P., Chang, Andrew,
and Lee, Whay Sing, "Exploiting Fine-Grain Thread Level Parallelism on
the MIT Multi-ALU Processor" , 25th Annual
International Symposium on Computer Architecture, Barcelona, Spain,
July 1998. pp 306-317. Abstract
- Keckler, Stephen W., Dally, William J., Chang, Andrew,
Carter, Nicholas P., and Lee, Whay Sing, "The MIT Multi-ALU Processor" , HotChips IX , Stanford, CA, August
1997. pp 1-7. Abstract
- Fillo, Marco, Keckler, Stephen W., Dally, William J., Carter, Nicholas
P., Chang, Andrew, Gurevich, Yevgeny,
and Lee, Whay S., "The
M-Machine Multicomputer" , International Journal
of Parallel Programming - Special Issue on Instruction-Level Parallel
Processing Part II . Vol 25, No 3, 1997 pp
183-212.
- Fillo, Marco, Keckler, Stephen W., Dally, William J., Carter, Nicholas
P., Chang, Andrew, Gurevich, Yevgeny,
and Lee, Whay S., "The
M-Machine Multicomputer" , Proceedings of the 28th
Annual International Symposium on Microarchitecture,
Ann Arbor, MI 1995. pp 146-156. Abstract
- Carter,
Nicholas P., Keckler, Stephen W., and Dally, William J., "Hardware Support for Fast Capability-based
Addressing", 6th International Conference on
Architectural Support for Programming Languages and Operating Systems
(ASPLOS VI). San Jose, CA, 1994.
- Keckler, Stephen W. and Dally, William J., "Processor Coupling: Integrating Compile Time and
Runtime Scheduling for Parallelism", 19th Annual
International Symposium in Computer Architecture, Queensland,
Australia, 1992.
- Carter, Nicholas P., "Processor Mechanisms for Software Shared
Memory", PhD Thesis, Masschusetts Institute of Technology, February 1999.
- Lee, Whay Sing, "Mechanisms for Efficient, Protected
Messaging", PhD Thesis, Masschusetts Institute of Technology, February 1999.
- Keckler, Stephen W., "Fast Thread Communication and Synchronization
Mechanisms for a Scalable Single Chip Multiprocessor",
PhD Thesis, Massachusetts Institute of Technology, June 1998.
- Chang, Andrew, "VLSI Datapath Choices: Cell-Based Versus Full-Custom" (Abstract , pdf , ps) , SM Thesis, Masschusetts Institute of Technology, February 1998.
Slides from
Presentation at Masterworks'98 (pdf)
Datafiles from Thesis Experiments (tgz)
- Klayman, Keith, "Design of the Configuration and Diagnostic Units
of the MAP Chip", MEng Thesis, Masschusetts Institute of Technology,
May 1997.
- Ma, Albert, "An I/O Controller for the MAP Chip", MEng Thesis, Masschusetts Institute of Technology, May 1997.
- Shultz, Andrew, "Advances in the M-Machine Runtime System", MEng Thesis, Masschusetts Institute of Technology, May 1997.
- Chatterjee, Sandeep, "Asynchronous Event Handling",
SM Thesis, Masschusetts Institute of Technology,
May 1996.
- Gupta, Parag, "Design and Implementation of the Integer Unit
Datapath of the MAP Cluster of the M-Machine", MEng Thesis, Masschusetts Institute of Technology, May 1996.
- Hartman, Daniel, "M-Machine Floating-Point Multiplier
Datapath", MEng Thesis, Masschusetts Institute of Technology, May 1996.
- Gurevich, Yevgeny, "The M-Machine Operating System", MEng Thesis, Masschusetts Institute of Technology, September 1995.
- Gurevich, Yevgeny, "An Assembler and Linker System for the M-Machine
Software Project", Advanced Undergraduate Project,
Massachusetts Institute of Technology, May, 1994.
- Keckler, Stephen W., "A Coupled Multi-ALU Processing Node for a Highly
Parallel Computer" , SM Thesis, Artificial
Intelligence Laboratory Technical Report 1355, Massachusetts Institute of
Technology, 1992.
- Dally, William J., Keckler, Stephen W., Carter, Nick,
Chang, Andrew, Fillo, Marco, and Lee, Whay S., "The M-Machine Instruction Set Reference Manual v1.55" ,
CVA Memo 59, 1997.
- Gupta, Parag, "The Design and Implementation of the Memory
Unit" , CVA Memo -
Preliminary Design Specification, Massachusetts Institute of Technology,
January 21, 1997.
- Keckler, Stephen W., "The Architecture of the MAP Floating Point
Unit" , CVA Memo -
Preliminary Design Specification, Massachusetts Institute of Technology,
January 20, 1996.
- Dally, William J., "The MAP Instruction Fetch Unit (IFU)" , CVA Memo - Preliminary Design Specification,
Massachusetts Institute of Technology, August 4, 1995.
- Keckler, Stephen W., "The Architecture of the MAP Synchronization
Stage" , CVA Memo -
Preliminary Design Specification, Massachusetts Institute of Technology,
February 15, 1995.
- Chang,
Andrew, "The Architecture of the RR Stage of the MAP
Pipeline" , CVA Memo -
Preliminary Design Specification, Massachusetts Institute of Technology,
February 14, 1995.
- Chang,
Andrew, "The Architecture of the Integer Execution Stage
of the MAP Pipeline" , CVA
Memo - Preliminary Design Specification, Massachusetts Institute of
Technology, February 14, 1995.
- Fillo, Marco, Keckler, Stephen W., Dally, William J., Carter, Nicholas
P., Chang, Andrew, Gurevich, Yevgeny,
and Lee, Whay S., "The
M-Machine Multicomputer" , Artificial Intelligence
Laboratory Memo 1532, Massachusetts Institute of Technology, 1995.
- Dally, William J., Keckler, Stephen W., Carter, Nick,
Chang, Andrew, Fillo, Marco, and Lee, Whay S., "The M-Machine Architecture v1.0" , CVA
Memo 58, 1995.
- Keckler, Stephen W., "The Importance of Locality in Scheduling and Load
Balancing for Multiprocessors", Concurrent VLSI
Architecture Memo 61, Massachusetts Institute of Technology, 1994.
- Keckler, Stephen W., "A Coupled Multi-ALU Processing Node for a Highly
Parallel Computer" , SM Thesis, Artificial
Intelligence Laboratory Technical Report 1355, Massachusetts Institute of
Technology, 1992.
- Dally, William J., Chang, Andrew., Chien, Andrew., Fiske, Stuart., Horwat, Waldemar., Keen,
John., Lethin, Richard., Noakes,
Michael., Nuth, Peter., Spertus, Ellen., Wallach, Deborah., and Wills, D. Scott.
"The J-Machine" .
Retrospective in 25 Years of the International Symposia on Computer Architecture
- Selected Papers. pp 54-58.
- Noakes, Michael D.,Wallach, Deborah, and Dally, William J., "The J-Machine Multicomputer: An Architectural
Evaluation", Twentieth Annual International
Symposium in Computer Architecture, San Diego, CA, 1993.
- Spertus, Ellen, Goldstein, Seth C.,Schauser, Klaus Erik Schauser., von Eiken, Thorsten., Culler, David E., and Dally, William J., "Evaluation of Mechanisms for Fine-Grained
Parallel Programs in the J-Machine and the CM-5", Twentieth
Annual International Symposium in Computer Architecture, San Diego,
CA, 1993.
- Dally, William J., "The
J-Machine: System Support for Actors", in Towards Open Information
Science, Editors, Hewitt, Carl and Agha, Gul, MIT Press, 1992.
- Dally, William J. and Fiske, J.A.
Stuart and Keen, John S. and Lethin, Richard A.
and Noakes, Michael D. and Nuth,
Peter R. and Davison, Roy E. and Fyler, Gregory
A., "The Message-Driven Processor: A Multicomputer
Processing Node with Efficient Mechanisms",
"IEEE Micro", April, 1992.
- Dally, William J. and others, The Message-Driven Processor: An Integrated Multicomputer Processing Element, Proceedings of the IEEE International Conference on
Computer Design: VLSI in Computers and Processors, IEEE Press, 1992.
- Lethin,
Richard A. and Dally, William J., "MDP Tools
and Methods", Proceedings of the International Conference on Computer
Design: VLSI in Computers and Processors, 1992.
- Nuth, Peter
R. and Dally, William J., "The J-Machine Network",
Proceedings of the International Conference on Computer Design: VLSI in
Computers and Processors, October, 1992.
- Dally, William J. and others,
"Design and Implementation of the Message-Driven Processor",
Proceedings of the 1992 Brown/MIT Conference on Advanced Research in VLSI
and Parallel Systems, MIT Press, March, 1992.
- Spertus, Ellen and Dally, William J. , "Experiences with Dataflow on a General-Purpose
Parallel Computer" , Proceedings of International
Conference on Parallel Processing, 1991.
- Dally, William J., "The
J-Machine System", in Artificial Intelligence at MIT: Expanding
Frontiers, editor Patrick Winston with Sarah A. Shellard, MIT Press, 1990.
- Noakes,
Michael and Dally, William J., "System
Design of the J-Machine",Sixth MIT
Conference of Advanced Research in VLSI, The MIT Press, 1990.
- Horwat, Waldemar and Chien, Andrew and Dally, William J. , "Experience
with CST:Programming and Implementation",
Proceedings of the ACM SIGPLAN 89 Conference on Programming Language
Design and Implementation, 1989.
- Chien, Andrew and Dally, William J., "CST: An
Object-Oriented Concurrent Language" Object-Based Concurrent
Programming Workshop, September, 1988, Conference held at San Diego, CA.
SIGPLAN Notices, February 1989.
- Dally, William J., Fine-Grain Message
Passing Concurrent Computers, Proceedings of the Third Conference on
Hypercube Concurrent Computers, Pasadena, CA, 1988.
- Dally, William J. and others, "Architecture of a Message-Driven Processor",Proceedings of the 14th International Symposium on Computer Architecture, 1987.
- Dally, William J. and Seitz, Charles L., "Deadlock
Free Message Routing in Multiprocessor Interconnection Networks", IEEE
Transactions on Computing, Volume C-36, May, 1987.
- Dally, William J. and Kajiya, James T., An Object Oriented
Architecture, Proceedings of the 12th International Symposium on Computer
Architecture, 1985.
- Kaneshiro, Shaun Yoshie, "Branch and Bound Search on the
J-Machine", SM Thesis, Massachusetts Institute of Technology,
Department of Electrical Engineering, September 1993.
- Nuth, Peter
R., "The Named-State Register File",
PhD Thesis, Artificial Intelligence Laboratory Technical Report 1459,
Massachusetts Institute of Technology, August 1993.
- Spertus, Ellen, "Execution of Dataflow Programs on General-Purpose
Hardware", SM Thesis, Massachusetts Institute of
Technology, Department of Electrical Engineering, August, 1992.
- Fatovic, Jerko, "A Ray Tracer for the J-Machine", SB
Thesis, Massachusetts Institute of Technology, Department of Electrical
Engineering, May, 1992.
- Lethin,
Richard A., A Simulator for the Message-Driven Processor, SM Thesis,
Massachusetts Institute of Technology, 1991.
- Horwat, Waldemar, Concurrent Smalltalk on the Message-Driven
Processor, SM Thesis, Massachusetts Institute of Technology, May 1989.
- Chao, Linda, "Architectural
Features of a Message-Driven Processor", SB Thesis, Massachusetts
Institute of Technology, May, 1987.
- Totty, Brian,
"An Operating Environment for the Jellybean Machine", SB Thesis,
Massachusetts Institute of Technology, Department of Electrical
Engineering and Computer Science, May, 1988.
- Horwat, Waldemar, "A Concurrent Smalltalk Compiler for
the Message-Driven Processor", MIT AI Memo, 545 Technology Sq.,
Cambridge, MA 02139, May, SB Thesis.
- Nuth, Peter
R., "The Named-State Register File: Implementation and
Performance", Concurrent VLSI Architecture Memo,
Massachusetts Institute of Technology, 1993.
- Horwat, Waldemar, "Revised CST Manual Version
?", CVA Memo #?. VERY WORTHWHILE (Note: this HREF points to a .ps
file which prints but gives trouble to ghostview).
- Spertus, Ellen and Dally, William J., "Experiments with Dataflow on a General-Purpose
Parallel Computer", Artificial Intelligence
Laboratory Technical Report 1272, Massachusetts Institute of Technology,
1991.
- An
experimental QCD code has been implemented on the J-machine by Richard Lethin and Robert Rippel in order to evaluate
communication and computation behavior (report in PostScript).
- Dally, William J., Dennison, Larry
R., Harris, David, Kan, Kinhong, and Xanthopoulos, Thucydides "The
Reliable Router: A Reliable and High-Performance Communication Substrate
for Parallel Computers," in Proceedings of the
First International Parallel Computer Routing and Communication Workshop,
Seattle WA, May 1994.
- Dally, William J., Dennison, Larry
R., Harris, David, Kan, Kinhong, and Xanthopoulos, Thucydides, "Architecture
and Implementation of the Reliable Router," in
Proceedings of Hot Interconnects II, Stanford CA, August 1994.
- Dennison,
Larry R., Dally, William J., and Xanthopoulos, Duke, "Low-Latency Plesiochronous Data Retiming," in Proceeding of the 1995 Advanced Research in VLSI Conference, Chapel
Hill NC, March 1995.
- Dennison,
Larry R., Lee, Whay S., and Dally, William J., "High-Performance Bidirectional Signalling in VLSI
Systems," in Proceedings of the 1993 Symposium on
Research on Integrated Systems, Seattle WA, January 1993.
- Dennison,
Larry R., "The Reliable Router: An Architecture for Fault
Tolerant Interconnect", PhD Thesis, Masschusetts Institute of Technology, June 1996.
- Xanthopoulos, Thucydides, "Fault Tolerant Adaptive Routing in Multicomputer
Networks", SM Thesis, Massachusetts Institute of
Technology, Department of Electrical Engineering, February, 1995.
- Dennison, Larry R., "Reliable Interconnection Networks for Parallel
Computers", SM Thesis, Masschusetts Institute of Technology, January 1991.
Chiang, Patrick, Dally, William J., and Lee, Ming-Ju, "A Monolithic Communications System",
2001 IEEE International Symposium on Circuits and Systems, Sydney, Australia,
May 6-9, 2001, paper 2145.
- Dally, William J., and Chang, Andrew, "The Role of Custom Design in ASIC Chips",
Proceedings of the 37th Design Automation Conference, Los Angeles, CA.
June 2000.
- Dally, William J., and Lacy, Steve, "VLSI Architecture: Past, Present, and
Future", Proceedings of the Advanced Research in
VLSI conference, Atlanta, GA, 1999.
- Fiske,
J. A. Stuart and Dally, William J., "Thread
Prioritization: A Thread Scheduling Mechanism For Multiple-Context
Parallel Processors," Future Generation Computer Systems, Vol.
11, No. 6, November 1995.
- Spertus, Ellen and Dally, William J., "Evaluating
the Locality Benefits of Active Messages," Proceedings of
Principles and Practice of Parallel Programming (PPOPP), Santa
Barbara, CA, July 19-21, 1995.
- Nuth, Peter
R. and Dally, William J., "The Named-State Register File: Implementation and
Performance", Proceedings of the 1st
International Symposium on High-Performance Computer Architecture,
Raleigh, NC, January 1995.
- Nuth, Peter R. and Dally, William J., "Named State and Efficient Context Switching",
in "Multithreading: A Summary of the State of the Art",
Edited by Robert A. Iannucci, Kluwer 1993.
- "International
Symposium on Computer Architecture 1992", by Keckler, Stephen W. and Dally, William J.. Scientific
Information Bulletin, Office of Naval Research Asian Office, Vol. 17,
No. 4, 1992.
- Knobe,
Kathleen B., "The Subspace Model: Shape-based Compilation for
Parallel Systems", PhD Thesis, Massachusetts
Institute of Technology, January 1997.
- Fiske, J. Stuart A., "Thread Scheduling Mechanims for Multiple Context
Parallel Processors", PhD Thesis, Artificial
Intelligence Laboratory Technical Report 1545, Massachusetts Institute of
Technology, June 1995.
- Keen, John S., "Logging and Recovery in a Highly Concurrent
Database"", PhD Thesis, Massachusetts
Institute of Technology, May 1994.
- Von Kapff,
Marcus Alexander, "Industry Assesment and
Market Analysis of Massively Parallel Computers", Master's Thesis,
Sloan School at Massachusetts Institute of Technology, May, 1993.
- Wallach, Deborah A., "PHD: A Hierarchical Cache Coherent Protocol",
SM Thesis, Masschusetts Institute of Technology,
September 1992.
vparikh1_stanford